Cordic method and architecture applied in vector rotation

ABSTRACT

A CORDIC method and a CORDIC architecture applied in vector rotation are disclosed. An elementary angles set is extended by representing the elementary angles as the arctangent of the sum of two single signed-power-of-two terms to an extended elementary angles set. A combination of elementary angles is found from the extended elementary angles set such that the residue angle error can be minimized. A quantized scaling factor is used to scale the combination of elementary angles after being micro-rotated.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a COordinate Rotational DIgital Computer (CORDIC) method and a CORDIC architecture applied in vector rotation, and more particularly, to a CORDIC method based on Extended Elementary-Angle Sets (EEAS) and Trellis-based Searching (TBS) and its architecture.

2. Description of Related Art

Currently, vector rotation is the kernel of various digital signal-processing applications, including discrete orthogonal transformations, lattice-based digital filtering, matrix computation, complex-valued number manipulation, etc. In X-Y coordinates one vector rotation operation can be expressed as:

$\begin{bmatrix} x_{out} \\ y_{out} \end{bmatrix} = {\begin{bmatrix} {\cos\;\theta} & {{- \sin}\;\theta} \\ {\sin\;\theta} & {\cos\;\theta} \end{bmatrix} \cdot \begin{bmatrix} x_{in} \\ y_{in} \end{bmatrix}}$

FIG. 1 shows hardware architecture used to implement the vector rotation operation, which requires two adders 11 and four multipliers 12. That is, the execution of one vector rotation operation will require executing two addition operations and four multiplication operations. The complexity of such an execution is too high. Reducing the wordlength can decrease the complexity. However, the SQNR will be increased accordingly.

The CORDIC algorithm is a well-known iterative method for the computation of vector rotation, which requires only one shift operation and one addition operation to perform a vector rotation operation. The CORDIC algorithm decomposes the rotation angle θ into a combination of pre-defined elementary angles as follows:

$\begin{matrix} {{\theta = {{\sum\limits_{i = 0}^{N - 1}{{\mu(i)}{a(i)}}} + ɛ}},} & (1) \end{matrix}$ where N is the number of elementary angles, μ={1, −1} is the rotation sequence which determines the direction of the i-th elementary angle of a(i)=tan⁻¹(2^(−i)), and ε denotes the residue angle.

Based on equation (1), the recurrence equations of the CORDIC algorithm can be written as

$\begin{matrix} \left\{ {\begin{matrix} {{x\left( {i + 1} \right)} = {{x(i)} - {{\mu(i)}{y(i)}2^{- i}}}} \\ {{y\left( {i + 1} \right)} = {{y(i)} + {{\mu(i)}{x(i)}2^{- i}}}} \end{matrix},} \right. & (2) \end{matrix}$ for i=0, 1, . . . , N−1. In practical fixed-point implementation, for data wordlength of W bits, no more than W iterations of the recurrence relation in equation (2) need be performed, i.e., N≦W. Also, the final values, x(N) and y(N), need to be scaled by an accumulated scaling factor expressed as follows:

$\begin{matrix} {P = {\left( {\prod\limits_{i = 0}^{N - 1}\sqrt{1 + 2^{{- 2}i}}} \right)^{- 1}.}} & (3) \end{matrix}$

In the above CORDIC algorithm, each elementary angle needs to be performed sequentially so as to complete the micro-rotation phase. However, in the applications where the rotation angles are known in advance, it would be advantageous to relax the sequential constraint on the micro-rotation phase. The angle recoding (AR) technique is done by extending the set of μ(i) from {1, −1} to {1, −1, 0}. By substituting μ(i)=0 into equation (2), one can skip the micro-rotation of the elementary angle a(i )=tan⁻¹(2^(−i)). Nevertheless, the AR technique imposes no restriction on the iteration number. Rotation angles of different values may need unequal numbers of iterations, which may lead to bus/timing alignment problems in VLSI circuits. Therefore, it is desired for the above CORDIC algorithm to be improved to mitigate and/or obviate the aforementioned problems.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a CORDIC method and a CORDIC architecture applied in vector rotation, which can effectively improve SQNR performance, reduce the number of iterations and decrease the hardware complexity.

In accordance with one aspect of the present invention, a CORDIC method applied in vector rotation is provided, which first extends an elementary angles set: S ₁={ tan⁻¹(a′*2^(−s′)):a′ε{−1,0,1},s′ε{0,1, . . . , N−1}}, by representing the elementary angles as the arctangent of the sum of two single signed-power-of-two (SPT) terms (a′*2^(−s′)) to an extended elementary angles set: s ₂={ tan⁻¹(a′ ₀*2^(−s′) ⁰ +a′ ₁*2^(−s′) ¹ ):a′ ₀ , a′ ₁ε{−1,0,1,},s′ ₀ ,s′ ₁ε{0,1, . . . , N−1}}, where N is the number of elementary angles. Next, a combination of elementary angles is found from the extended elementary angles set such that the residue angle error:

$ɛ_{m} = \left| {\theta - {\sum\limits_{j = 0}^{R_{m} - 1}{\tan^{- 1}\left\lbrack {\left. {{{a_{0}(j)}*2^{- {S_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {S_{1}{(j)}}}}} \right|,} \right.}}} \right.$

can be minimized, where θ is a target angle; R_(m) is the maximum iteration number; j denotes the iteration index; s₀(j), s₁(j) ε{0, 1, . . . , N−1} are the rotational sequences; a₀(j), a₁(j) control the direction of j-th micro-rotation of 2^(−S) ⁰ ^((j)), 2^(−S) ¹ ^((j)). Then, a quantized scaling factor is used to scale the combination of elementary angles determined in step (B) after being micro-rotated.

In accordance with another aspect of the present invention, a CORDIC processor applied in vector rotation is provided for performing micro-rotational phase operations:

$\left\{ {\begin{matrix} {{x\left( {j + 1} \right)} = {{x(j)} - {\left\lbrack {{{a_{0}(j)}*2^{- {S_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {S_{1}{(j)}}}}} \right\rbrack{y(j)}}}} \\ {{y\left( {j + 1} \right)} = {{y(j)} + {\left\lbrack {{{a_{0}(j)}*2^{- {S_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {S_{1}{(j)}}}}} \right\rbrack{x(j)}}}} \end{matrix},{and}} \right.$ scaling phase operations:

$\left\{ {\begin{matrix} {{\overset{\sim}{x}\left( {m + 1} \right)} = {{\overset{\sim}{x}(m)} + \left\lbrack {{{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}}} + {{k_{1}(m)} \cdot 2^{- {q_{1}{(m)}}}}} \right\rbrack}} \\ {{\overset{\sim}{y}\left( {m + 1} \right)} = {{\overset{\sim}{y}(m)} + \left\lbrack {{{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}}} + {{k_{1}(m)} \cdot 2^{- {q_{1}{(m)}}}}} \right\rbrack}} \end{matrix}.} \right.$ In the CORDIC processor, a first register is provided for temporarily storing x(i) or {tilde over (x)}(m). A second register is provided for temporarily storing y(i) or {tilde over (y)}(m). First and second barrel shifters have input terminals connected to output terminals of the first register. Third and fourth barrel shifters have input terminals connected to output terminals of the second register. A first multiplexer has a first input terminal connected to an output terminal of the first barrel shifter, and a second input terminal connected to an output terminal of the third barrel shifter. A second multiplexer has a first input terminal connected to an output terminal of the second barrel shifter, and a second input terminal connected to an output terminal of the fourth barrel shifter. A third multiplexer has a first input terminal connected to the output terminal of the first barrel shifter, and a second input terminal connected to an output terminal of the third barrel shifter. A fourth multiplexer has a first input terminal connected to the output terminal of the second barrel shifter, and a second input terminal connected to the output terminal of the fourth barrel shifter. A first adder/subtractor has two input terminals connected to output terminals of the first and second multiplexers, respectively. A second adder/subtractor has two input terminals connected to output terminals of the first adder/subtractor and first register, respectively, and an output terminal connected to an input terminal of the first register. A third adder/subtractor has two input terminals connected to output terminals of the third and fourth multiplexers, respectively. A fourth adder/subtractor has two input terminals connected to output terminals of the third adder/subtractor and second register, respectively, and an output terminal connected to an input terminal of the second register. A control unit controls the first to fourth barrel shifters, the first to fourth multiplexers, and the first to fourth adders/subtractors to perform the CORDIC operation iteratively.

In accordance with still another object of the present invention, a CORDIC architecture applied in vector rotation is provided having (R_(m)+R_(s)) CORDIC processors connected in cascade form, in which the R_(m) leading processors are used in the micro-rotation phase and the following R_(s) processors are used in the scaling phase.

Other objects, advantages, and novel features of the invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a conventional hardware architecture for implementing vector rotation;

FIG. 2 is the flowchart of the CORDIC method in accordance with the present invention;

FIG. 3 schematically illustrates the initialization and transfer path of the TBS algorithm;

FIG. 4 schematically illustrates an accumulation step example in the TBS algorithm;

FIG. 5 schematically illustrates a selection step example in the TBS algorithm;

FIG. 6 schematically illustrates a trace back step example in the TBS algorithm;

FIG. 7 shows a CORDIC architecture hardware implementation in accordance with the present invention;

FIG. 8 shows another CORDIC architecture hardware implementation in accordance with the present invention;

FIG. 9 shows a performance comparison between EEAS and EES; and

FIG. 10 shows a performance comparison between the TBS method and the Greedy method.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 2 shows the flowchart of the CORDIC method applied in vector rotation in accordance with the present invention. As shown the present method includes the following three stages: (S1) extending the elementary angle set (EAS) to an extended elementary angle set (EEAS) for executing the CORDIC algorithm; (S2) using a Trellis-based Searching (TBS) method to find a combination of elementary angles from the elementary angles of the EEAS such that the residue angle is minimum; and (S3) using an extended type-II (ET-II) scaling operation to perform the scaling correction.

To depict the EEAS in the first stage, a parameter R_(m) is employed to be the maximum iteration number in the AR technique. Therefore, the AR problem can be summarized as:

Given a target angle θ and the maximum iteration number R_(m), find the rotation sequence μ(i) ε{1,−1,0} for 0≦i≦N−1, such that the residue angle error:

$\begin{matrix} {{\left. {ɛ_{m} \equiv} \middle| {\theta - {\sum\limits_{i = 0}^{N - 1}{{\mu(i)}{a(i)}}}} \right| = \left| {\theta - {\sum\limits_{i = 0}^{N - 1}{{\mu(i)}\;{\tan^{- 1}\left( 2^{- i} \right)}}}} \right|},} & (4) \end{matrix}$ is minimized subject to the constraint:

$\begin{matrix} {\sum\limits_{i = 0}^{N - 1}\left| {\mu(i)} \middle| {\leq {R_{m}.}} \right.} & (5) \end{matrix}$ To facilitate the derivation of the present EEAS scheme, the AR problem described above is rewritten in an alternative form. The reformulation is done by removing the redundant iterations of μ(i)=0 in equation (4), changing the variables and index, and using the equality ±tan⁻¹(A)=tan⁻¹(±A). Then, the equations (4) and (5) can be recast in a single compact form as:

$\begin{matrix} {{ɛ_{m} = {\left| {\theta - {\sum\limits_{j = 0}^{R_{m} - 1}{\tan^{- 1}\left( {{a(j)}*2^{- {s{(j)}}}} \right)}}} \right| = \left| {\theta - {\sum\limits_{j = 0}^{R_{m} - 1}{\theta^{\prime}(j)}}} \right|}},} & (6) \end{matrix}$ where j(0≦j≦R_(m)−1) denotes the iteration index; s(j) ε{0, 1, . . . , N−1} is the rotational sequence that determines the micro-rotation angle in the j-th iteration; a(j) ε{−1, 0, 1} is the directional sequence that controls the direction of the j-th micro-rotation of 2^(−s(j)); θ′(j) is the j-th micro-rotation angle and defined as θ′(j)≡ tan⁻¹(a(j)*2^(−s(j))).

Therefore, equation (6) shows that the AR problem is finding the combination of elements from a set, which consists of all possible values of θ′(j), so that ε_(m) can be minimized. Such a set is called the elementary angles set (EAS) S₁, and is defined as S ₁={ tan⁻¹(a′*2^(−s′)):a′ε{−1,0,1},s′∈{0,1, . . . , N−1}}.  (7) By observing equation (7), it is seen that the EAS S1 is comprised of an arctangent of single signed-power-of-two (SPT) term, i.e., tan⁻¹(a′*2^(−s′)). By representing the elementary angles as the arctangent of the sum of two SPT terms, the EAS S₁ can be extended to an extended elementary angles set (EEAS) S₂ as follows: s ₂={ tan⁻¹(a′ ₀*2^(−s′) ⁰ +a′ ₁*2^(−s′) ¹ ):a′ ₀ ,a′ ₁ε{−1,0,1{,s′ ₀ ,s′ ₁ε{0,1, . . . ,N−1}}.  (8) Based on the EEAS S₂ developed in equation (8), the recurrence equations of the CORDIC algorithm can be modified as:

$\begin{matrix} \left\{ \begin{matrix} {{x\left( {j + 1} \right)} = {{x(j)} - {\left\lbrack {{{a_{0}(j)}*2^{- {S_{0}{(j)}}}} + {{a_{1}(J)}*2^{- {S_{1}{(j)}}}}} \right\rbrack{y(j)}}}} \\ {{{y\left( {j + 1} \right)} = {{y(j)} + {\left\lbrack {{{a_{0}(j)}*2^{- {S_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {S_{1}{(j)}}}}} \right\rbrack{x(j)}}}},} \end{matrix} \right. & (9) \end{matrix}$ for 0≦j≦R_(m)−1, where a₀(j), a₁(j), s₀(j) and s₁(j) denote the parameters to control the j-th micro-rotation of the elementary angle of tan⁻¹(a₀(j)*2^(−S) ⁰ ^((j))+a₁(j)*2^(−S) ¹ ^((j))).

With the above EEAS S₂ and given θ and R_(m), it is desired to find the parameters of a₀(j), a₁(j), s₀(j) and s₁(j) (i.e., the combination of elementary angles from EEAS S₂), such that the residue angle error:

$\begin{matrix} {ɛ_{m} = \left| {\theta - {\sum\limits_{j = 0}^{R_{m} - 1}{\tan^{- 1}\left\lbrack {\left. {{{a_{0}(j)}*2^{- {S_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {S_{1}{(j)}}}}} \right|,} \right.}}} \right.} & (10) \end{matrix}$ can be minimized.

In the second stage of processing, the TBS algorithm is employed to find the combination of elementary angles, wherein Z(S₂) denotes the number of the elementary angles in the extended set S₂, and each distinct elementary angle in the set is expressed as r(k), for 1≦k≦Z(S2), i.e., S₂={r(1), r(2), . . . , r(Z(S2))}. Moreover, in the TBS algorithm, there are Z(S₂) states in each step. For the k-th state (1≦k≦Z(S₂)) of the i-th search step, a cumulative angle Φ(i,k) is used to denote the best approximation of angle θ in the k-th state up to the i-th step. The TBS algorithm can be described as follows:

(1) Initialization Step:

The TBS algorithm is started by setting all Φ(i,k) as the corresponding elementary angles, that is: Φ(1,k)=r(k) for all k.  (11) Taking Z(S₂)=15 as an example, the initialization and transfer paths of the TBS algorithm are illustrated in FIG. 3. (2) Accumulation Step

A path in the trellis, which leaves the k-th state at the i-th step and enters the k-th state at the (i+1)-th step, corresponds to an operation of Φ(i,k)+r(k′). For all paths, the appended angle of Φ(i,k)+r(k′) becomes the candidate for Φ(i+1,k′). As shown in FIG. 4, from a given state at step i=i*, the paths can diverge to all the states at the next search step (i*+1). Namely, there are Z(S₂) paths, carrying the corresponding appended angles of Φ(i,k)+r(k′) for all k, entering the k′-th state at the (i*+1)-th step. Then, those appended angles form the candidate set for the cumulative angle of Φ(i*+1,k′).

(3) Comparison and Selection Step

The TBS algorithm involves calculating and minimizing the difference between the target angle θ and Φ(i,k) for all k at each search step i. To be specific, Φ(i+1,k) is determined by: Φ(i+1,k)=min{|Φ(i,k*)+r(k)−θ|:1≦k*≦Z(S ₂)}.  (12) Then, the selected path is denoted as the surviving path. After calculating all the cumulative angles Φ(i,k) for all k, their corresponding surviving paths can be obtained. Continuing in this manner and moving to the (i+1)-th step until reaching the maximum iteration number (i=Rm), Φ(R_(m),k) can be obtained for 1≦k≦Z(S₂). Consider the example, in which i=2 and k=12. The process of equation (12) is illustrated in FIG. 5. From those 15 paths entering the 12th state at the 3rd search step, the path, of which the appended angle Φ(2, j)+r(12) is closest to θ=π/3, is selected as the surviving path. In this case, the third path (k*=3), which is marked by the solid line, is selected. Then, the resultant angle is assigned to Φ(3,12) for the subsequent search process. (4) Determination of the Global Result and Trace Back Step

After calculating the cumulative angles for all states at the last search step, i.e., Φ(R_(m),k) for 1≦k≦Z(S2), the next procedure for the TBS algorithm is to determine the global result, θ_(TBS). Similar to the determination of the surviving path, the θ_(TBS) is decided as follows: θ_(TBS)=min{|Φ(R _(m) ,K′)−θ|:1≦k′≦Z(S ₂)}.  (13) Next, all the micro-rotations can be determined by tracing back from the state, whose corresponding Φ(R_(m),k) is the best approximation of θ, along with its surviving backward path.

The procedure for trace back is illustrated in FIG. 6. All the surviving paths for each state at each step (except i=1) are represented by the dashed line. First, Φ(4,13) is selected as the global result. Then, it is traced along the surviving path that connects the 13th state at the final backward step. Next, it finds the state from which the surviving path leaves in the previous step. By doing the process repeatedly, the global surviving path of the TBS algorithm can be determined, as marked by the solid line in. By traveling along the surviving global path, the algorithm is able to find the visited states and read all the micro-rotation angles that form the global result θ_(TBS). In this case, Φ(4,13)=r(9)+r(13)+r(2)+r(13), which is the best approximation of angle θ generated by the present TBS algorithm.

When considering that each micro rotation will scale up the norm of a vector, in the known type-II scaling operation, the accumulated scaling factor P is quantized as:

$\begin{matrix} {{\hat{p} = {\prod\limits_{m = 0}^{R_{s} - 1}\;\left( {1 + {{k(m)} \cdot 2^{q{(m)}}}} \right)}},} & (14) \end{matrix}$ where {circumflex over (P)} denotes the quantized value of P, k(m)ε{1,−} and q(m)ε{0,1, . . . , W−1}, R_(s) is the counterpart of R_(m) in the micro-rotation phase, determining the number of iterations in the scaling phase. With this type-II scaling operation, and by increasing the number of possible values that can be represented by (1+k(m)·2^(−q(m))), we obtain a similar derivation of the EEAS scheme that employs one extra SPT term in equation (14):

$\begin{matrix} {{\hat{P} = {\prod\limits_{m = 0}^{R_{s} - 1}\;\left( {1 + {{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}}} + {{k_{1}(m)} \cdot 2^{- {q_{1}{(m)}}}}} \right)}},} & (15) \end{matrix}$ where k₀(m)ε{1,−1,0}, k₁(m)ε{1,−1,0}, q₀(m)ε{0,1, . . . , W−1}, and q₁(m)ε{0,1, . . . , W−1}.

By doing so, it is expected to obtain more accurate approximations of P. The scaling operation can be accomplished within R_(s), iterations by using the recurrence equations:

$\begin{matrix} {\;\left\{ {\begin{matrix} {{\overset{\sim}{x}\left( {m + 1} \right)} = {{\overset{\sim}{x}(m)} + \left\lbrack {{{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}}} + {{k_{1}(m)} \cdot 2^{- {q_{1}{(m)}}}}} \right\rbrack}} \\ {{\overset{\sim}{y}\left( {m + 1} \right)} = {{\overset{\sim}{y}(m)} + \left\lbrack {{{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}}} + {{k_{i}(m)} \cdot 2^{- {q_{1}{(m)}}}}} \right\rbrack}} \end{matrix},} \right.} & (16) \end{matrix}$ wherein the initial settings for the scaling phase are set as {tilde over (x)}(0)=x(R_(m)) and {tilde over (y)}(0)=y(R_(m)).

FIG. 7 shows a hardware implementation of the CORDIC architecture applied in vector rotation according to the present invention, which is an iterative CORDIC processor. It consists of a control unit 701, first and second registers 711 and 712, first to fourth barrel shifters 721˜724, first to fourth multiplexers 731˜734, first to fourth adders/subtracters 741˜744.

The first register 711 is provided for temporarily storing x(i) or {tilde over (x)}(m), and its output terminal is connected to the first and second barrel registers 721 and 722, and its input terminal is connected to the second adder/subtracter 742. The second register 712 is provided for temporarily storing y(i) or {tilde over (y)}(m), and its output terminal is connected to the third and fourth barrel registers 723 and 724, and its input terminal is connected to the fourth adder/subtractor 744.

The output terminal of the first barrel register 721 is connected to the first input terminal of the first multiplexer 731 and the third multiplexer 733. The output terminal of the second barrel register 722 is connected to the first input terminal of the second multiplexer 732 and the fourth multiplexer 734. The output terminal of the third barrel register 723 is connected to the second input terminal of the first multiplexer 731 and the third multiplexer 733. The output terminal of the fourth barrel register 724 is connected to the second input terminal of the second multiplexer 732 and the fourth multiplexer 734.

The output terminals of the first and second multiplexers 731 and 732 are connected to the input terminals of the first adder/subtractor 741. The output terminal of the first adder/subtractor 741 is connected to the input terminal of the second adder/subtractor 742. The output terminals of the third and fourth multiplexers 733 and 734 are connected to the input terminals of the third adder/subtractor 743. The output terminal of the third adder/subtractor 743 is connected to the input terminal of the fourth adder/subtractor 744. The output terminals of the second and fourth adders/subtractors 742 and 744 are connected to the input terminals of the first and second register 711 and 712, respectively.

The control unit 701 is provided to control the first to fourth barrel shifters 721˜724, the first to fourth multiplexers 731˜734, and the first to fourth adders/subtractors 741˜744, so as to implement the CORDIC algorithm. Two separate phases are performed to complete a single CORDIC rotation, i.e., the micro-rotational phase and the scaling phase. In the micro-rotational phase, under the control of the control unit 701, the first and second barrel shifters 721 and 722 are shifted by s₁(i) and s₀(i) bits, respectively. The third and fourth barrel shifters 723 and 724 are shifted by s₀(i) and s₁(i) bits, respectively. The second input terminals of the first and second multiplexers 731 and 732 are switched to connect to their output terminals thereof, respectively. The first input terminals of the third and fourth multiplexers 733 and 734 are switched to connect to their output terminals thereof, respectively. The control unit 701 uses a₀(i) and a₁(i) to control first to fourth adders/subtracters 741˜744, so as to perform addition and subtraction.

In the scaling phase, under the control of the control unit 701, the first and second barrel shifters 721 and 722 are shifted by q₁(m) and q₀(m) bits, respectively. The third and fourth barrel shifters 723 and 724 are shifted by q₀(m) and q₁(m) bits, respectively. The first input terminals of the first and second multiplexers 731 and 732 are switched to connect to their output terminals thereof, respectively. The second input terminals of the third and fourth multiplexers 733 and 734 are switched to connect to their output terminals thereof, respectively. The control unit 701 uses k₀(m) and k₁(m) to control the first to fourth adders/subtracters 741˜744, so as to perform addition and subtraction.

By unfolding the iterative implementation of the above CORDIC processor, a parallel structure can be obtained as depicted in FIG. 8. The structure is composed of (R_(m)+R_(s)) CORDIC processors 81 connected in cascade form, in which the R_(m) leading processors 81 perform the micro-rotations and the following R_(s) processors 81 execute the scaling operations. Each CORDIC processor 81 performs one iteration as specified in FIG. 7.

In view of the foregoing, it is known that the present invention performs the CORDIC algorithm by extending EAS to EEAS. As shown in FIG. 9 that gives the comparison of the maximum iteration number and residue angle error between EEAS and EAS, it is known that EEAS can have a smaller residue angle error with less iteration number. FIG. 10 shows an experimental result in which the TBS method requires a smaller iteration number than the conventional Greedy method, and the combination of EEAS and TBS methods can further reduce the iteration number.

Although the present invention has been explained in relation to its preferred embodiment, it is to be understood that many other possible modifications and variations can be made without departing from the spirit and scope of the invention as hereinafter claimed. 

1. A CORDIC processor applied in vector rotation for performing micro-rotational phase operations and scaling phase operations, -the processor comprising: a first register for temporarily storing an X coordinate of input and output vectors of the processor; a second register for temporarily storing a Y coordinate of input and output vectors of the processor; first and second barrel shifters having input terminals connected to output terminals of the first register; third and fourth barrel shifters having input terminals connected to output terminals of the second register; a first multiplexer having a first input terminal connected to an output terminal of the first barrel shifter, and a second input terminal connected to an output terminal of the third barrel shifter; a second multiplexer having a first input terminal connected to an output terminal of the second barrel shifter, and a second input terminal connected to an output terminal of the fourth barrel shifter; a third multiplexer having a first input terminal connected to the output terminal of the first barrel shifter, and a second input terminal connected to an output terminal of the third barrel shifter; a fourth multiplexer having a first input terminal connected to the output terminal of the second barrel shifter, and a second input terminal connected to the output terminal of the fourth barrel shifter; a first adder/subtractor having two input terminals connected to output terminals of the first and second multiplexers, respectively; a second adder/subtractor having two input terminals connected to output terminals of the first adder/subtractor and first register, respectively, and an output terminal connected to an input terminal of the first register; a third adder/subtractor having two input terminals connected to output terminals of the third and fourth multiplexers, respectively; a fourth adder/subtractor having two input terminals connected to output terminals of the third adder/subtractor and second register, respectively, and an output terminal connected to an input terminal of the second register; and a control unit for controlling the first to fourth barrel shifters, the first to fourth multiplexers, and the first to fourth adders/subtractors to perform the micro-rotational phase operations and scaling phase operations of the CORDIC processor iteratively.
 2. The processor as claimed in claim 1, wherein, the micro-rotational phase operation is performed by the recurrence equations: $\quad{\quad\begin{matrix} {{x\left( {j + 1} \right)} = {{x(j)} - {\left\lbrack {{{a_{0}(j)}*2^{- {s_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {s_{1}{(j)}}}}} \right\rbrack{y(j)}}}} \\ {{{y\left( {j + 1} \right)} = {{y(j)} + {\left\lbrack {{{a_{0}(j)}*2^{- {s_{0}{(j)}}}} + {{a_{1}(j)}*2^{- {s_{1}{(j)}}}}} \right\rbrack{x(j)}}}},} \end{matrix}}$ for 0≦j≦R_(m−1), where R_(m) is the maximum iteration number for the micro-rotational phase operation, a₀(j), a₁(j), s₀(j) and s₁(j) are control parameters for the micro-rotational phase operation, x(j) and y(j) denote the X and Y coordinates of output vector of the vector rotation, and x(0) and y(0) denote the X and Y coordinates of input vector of the vector rotation, and wherein the scaling phase operation is performed by using recurrence equations: $\quad\begin{matrix} {{\overset{\sim}{x}\left( {m + 1} \right)} = {{\overset{\sim}{x}(m)} + \left\lbrack {{{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}}} + {{k_{1}(m)} \cdot 2^{- {q_{1}{(m)}}}}} \right\rbrack}} \\ {{\overset{\sim}{y}\left( {m + 1} \right)} = {{\overset{\sim}{y}(m)} + {\left\lbrack {{k_{0}(m)} \cdot 2^{- {q_{0}{(m)}}} \cdot {+ {k_{1}(m)}} \cdot 2^{- {q_{0}{(m)}}}} \right\rbrack.}}} \end{matrix}$ for 0≦m<R_(s), where R_(s) is the maximum iteration number for the scaling phase operation, {tilde over (x)}(m) and {tilde over (y)}(m) are the X and Y coordinates of output vector of the vector rotation, {tilde over (x)}(0) and {tilde over (y)}(0) are the X and Y coordinates of input vector of the vector rotation, and k₀(j), k₁(j), q₀(j) and q₁(j) are control parameters for the scaling phase operation.
 3. The processor as claimed in claim 2, wherein, in the micro-rotational phase, the first and second barrel shifters are shifted by s₁(i) and s₀(i) bits, respectively; the third and fourth barrel shifters are shifted by s₀(i) and s₁(i) bits, respectively; the second input terminals of the first and second multiplexers are switched to connect to their output terminals, respectively; the first input terminals of the third and fourth multiplexers are switched to connect to their output terminals, respectively; and the first to fourth adders/subtractors perform addition and subtraction under the control of a₀(i) and a₁(i).
 4. The processor as claimed in claim 2, wherein, in the scaling phase, the first and second barrel shifters are shifted by q₁(m) and q₀(m) bits, respectively; the third and fourth barrel shifters are shifted by q₀(m) and q₁(m) bits, respectively; the first input terminals of the first and second multiplexers are switched to connect to their output terminals, respectively; the second input terminals of the third and fourth multiplexers are switched to connect to their output terminals, respectively; and the first to fourth adders/subtractors perform addition and subtraction under the control of k₀(m) and k₁(m).
 5. A CORDIC architecture applied in vector rotation comprising (R_(m)+R_(s)) CORDIC processors as claimed in claim 1 connected in cascade form, in which the R_(m) leading processors are used in the micro-rotational phase and the following Rs processors are used in the scaling phase. 